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[CS.AI] AUTOGATE: LLM-Based Automated Clock Gating Framework

Published at: 2026-06-18 22:00 Last updated: 2026-06-20 13:49
#Machine Learning #optimization #Open Source

AUTOGATE introduces the first agentic framework for industry-grade RTL power optimization, enabling workload-aware clock-gating optimization across large hierarchical codebases. Fine-grain clock gating (FGCG) is effective in reducing dynamic power, yet current FGCG optimization flows remain largely manual. Existing LLM-based RTL optimization approaches face two key drawbacks: the inability to process long waveform traces spanning millions of cycles and the challenge of scaling optimization to large hierarchical codebases while preserving correctness.

AUTOGATE bridges waveform-level analysis and RTL rewriting through a Machine Learning (ML)-LLM co-design. We develop an ML-based clustering algorithm that distills raw toggling traces into compact, structured representations to guide LLM-based RTL rewriting. This approach allows for accurate identification and application of clock-gating opportunities without requiring LLMs to process raw waveform data directly. To enhance scalability, AUTOGATE employs a hierarchical multi-agent architecture that decomposes large designs into independently optimizable modules, enabling coordinated optimization across deep design hierarchies.

We evaluate AUTOGATE on a diverse set of designs, from small RTL designs to large industrial-grade codebases. Experimental results demonstrate that AUTOGATE consistently reduces dynamic power relative to baselines. Across the small-design suite, AUTOGATE achieves an average dynamic power reduction of 49.31%. For industry-scale designs, it realizes 19.34% and 7.96% dynamic power reductions on NVDLA and BlackParrot, respectively, and up to 6.86% on highly optimized proprietary production designs.

Blogger's Review: AUTOGATE's innovative ML-LLM co-design overcomes the limitations of traditional clock gating optimization, showcasing a perfect balance between efficiency and scalability. This new solution offers the industry a fresh perspective on automated tools in chip design, with significant results in dynamic power reduction highlighting its immense potential.

Original Source: https://arxiv.org/abs/2606.17461

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