Abstract
The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability.
Building upon this formulation, four interlocking contributions are presented:
- Bayesian Probabilistic Risk Model: This model maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound.
- Safety-Gated Decision Architecture: Provides a provable post-assembly failure probability guarantee.
- Uncertainty-Aware Disposition Boundaries: Derived from Bayes-optimal decision theory.
- Constrained Closed-Loop Feedback Mechanism: Delivers consistent model improvement without violating reliability constraints.
A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate thresholds.
Blogger's Review: This paper theoretically bridges a significant gap in testing methodologies for chiplet-based AI systems. The proposed KGRD screening approach offers a novel perspective on reliability assessment, highlighting its potential and challenges in practical applications.