Field‑programmable gate arrays (FPGAs) offer high‑throughput neural‑network inference thanks to their parallel fabric, yet most deployment pipelines either accelerate multiply‑accumulate units or map quantized models to lookup tables (LUTs). DiffLUT‑Net introduces a native FPGA network built entirely from six‑input LUTs and trains it from scratch in an end‑to‑end fashion.
The key idea is to jointly learn the 64 truth‑table entries of each LUT and the source signal for each of its six input ports. A differentiable LUT relaxation treats the discrete truth table as a continuous probability distribution, while a hardware source‑selection module lets the network dynamically choose which predecessor signal drives each port during training.
After training, both the truth tables and the connections are discretized via thresholding, unused logic cells are pruned, and the resulting network can be emitted directly as synthesizable Verilog without any additional mapping steps.
Experiments on five public benchmarks show that DiffLUT‑Net achieves favorable accuracy‑resource trade‑offs, delivering comparable accuracy with substantially lower resource consumption.
The implementation is open‑source at https://github.com/TUDa-HWAI/DiffLUT-Network, enabling reproducibility and further research.
Review: By learning LUT functions together with sparse connectivity, DiffLUT‑Net provides a practical route to compact FPGA‑native inference and opens new possibilities for hardware‑aware neural‑network design.