This work introduces a reliability‑aware quantized weight packing scheme for systolic‑array based edge DNN accelerators. A sensitivity‑driven mixed‑precision quantization framework assigns per‑layer bit‑widths according to their impact on overall accuracy, while enforcing symmetric precision between weights and activations. A deterministic register‑level packing strategy then merges multiple heterogeneous operand pairs into fixed‑width register words, enabling SIMD‑within‑a‑register (SWAR) style parallelism that reduces both memory footprint and execution cycles. To improve fault resilience, the most significant bits (MSBs) of critical layers are selectively replicated into unused register bits, achieving TMR‑like protection with minimal overhead. A systolic‑array simulation platform evaluates the packing and fault‑tolerance mechanisms under realistic conditions. Benchmarks on AlexNet, VGG‑11 and ResNet‑18 report up to 62% memory reduction, up to 56% MAC operation reduction, and markedly better accuracy resilience under fault injection compared with baseline and fully protected models.
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