Large language model (LLM) agents are being applied to chip design, yet most approaches operate directly at the RTL level. We investigate whether leveraging higher‑level abstractions can lead to better designs. Four flows are compared: Direct RTL Design, Agent‑based HLS Design, Post‑Compiler HLS Refinement, and Post‑HLS RTL Refinement. By combining Agent‑based HLS with RTL Refinement we obtain AHRR (Agent‑based HLS with RTL Refinement). FPGA is used as a practical, easy‑to‑deploy platform for end‑to‑end evaluation, and the trade‑offs studied are largely technology‑agnostic. Across an 11‑task benchmark suite, AHRR achieves a geometric‑mean speedup of $2.6\times$ over Direct RTL Design. Case studies reveal that HLS distills design knowledge into abstractions that agents can exploit, while RTL refinement recovers low‑level optimization opportunities. Together these results make AHRR a promising workflow for agentic chip design. The code and evaluation artifacts are available at https://github.com/ZijD/AHRR.
Review: AHRR’s combination of high‑level abstraction and fine‑grained RTL tuning showcases the potential of agents in hardware design, pointing toward more automated and efficient chip development pipelines.