2D-FET-Bench V2 is an executable benchmark for field‑effect transistor (FET) layout on exfoliated two‑dimensional flakes. Each task supplies contour coordinates extracted from microscopy and a textual device specification; the agent must emit typed polygon and path operations and render them to a GDSII file. A deterministic verifier checks that polygons correctly implement contacts, gates and other structures while preserving the original contour points, and an integrity check ensures the supplied outlines remain unchanged. The benchmark contains 128 tasks, including plain flakes, hole‑containing flakes and multi‑flake scenarios; scripted reference layouts solve all tasks, proving solvability.
We evaluate six large models and seven workflow/scaffold variants of GPT5.6‑Luna, allowing up to five attempts per task. The best configuration, GPT5.6‑Luna with ReAct‑3, achieves a pass@1 of 62.3%, task coverage (solved at least once) of 80.5%, and consistency (solved in all five attempts) of 43.8%. Compared with a single‑pass Plan‑and‑Execute approach, ReAct‑3 uses 2.46× more tokens but improves pass@1 by 27.0 points.
An expert audit sampled one verifier‑passing layout per covered task across the five ReAct‑3 variants; acceptance rates ranged from 56.4% to 63.5%. The benchmark isolates geometric and structural FET layout construction, offering a quantitative measure of language‑model capability in spatial reasoning and micro‑electronics design.
Review