Recent studies have introduced reinforcement learning with verifiable rewards (RLVR) that enable large language models (LLMs) to generate high‑quality RTL circuits from natural‑language specifications. Existing approaches collapse power, performance, and area (PPA) objectives into a single scalar reward, making it hard to produce diverse Pareto‑optimal solutions across trade‑offs such as low power, low latency, and small area. In real designs the relative importance of each objective varies with product requirements, so offering a diverse, high‑quality candidate set allows designers to pick a preferred compromise later.
This work is the first to propose a learning method for LLM‑based circuit generation that optimizes the quality and diversity of the entire set of circuits obtained through multiple generations in the PPA space, rather than the quality of a single circuit. The method consists of: (1) a generation‑based training pipeline that reformulates improving the coverage of the whole Pareto solution set into a sequential circuit generation problem; (2) a reward function based on Hypervolume Contribution (HVC) that measures how much a newly generated circuit contributes to the Pareto front.
Evaluation on the RTLLM v2 benchmark shows that the proposed approach achieves a 13.3% relative hypervolume improvement over a baseline without PPA optimization and a 14.4% gain over a single‑objective reinforcement learning method, while also demonstrating superior circuit diversity.
Review: By converting Pareto coverage into a sequential generation task and introducing an HVC‑based reward, the paper effectively enhances multi‑objective performance of LLM‑generated RTL circuits, offering a more flexible solution for practical hardware design.