The design pace of 6G will outstrip the time needed to build it. AI‑driven search can already propose physical‑layer algorithms at machine speed, yet moving a single algorithm onto embedded baseband silicon remains a specialist task. Silicon imposes strict memory and numeric limits and reveals cost structures absent in GPU‑only flows; a design process that never runs on the target sees neither. We present an agentic workflow where a large language model (LLM) coding agent implements algorithms on a commercial baseband SoC, optimizes them down to vector assembly, and validates them on silicon. The agent is guided by a knowledge base of measured platform facts, checked at every step against immutable evaluators, and metered per phase. We showcase the workflow on the open 6G4All platform by porting an AI‑discovered orthogonal time frequency space (OTFS) detector portfolio. Twelve kernels run cycle‑exactly on silicon; their optimized versions take 18k‑405k cycles (30‑660 µs) per frame. A new detector shaped by the chip’s measured costs uses 13.9% fewer cycles than the direct port while matching error rate, with a performance edge that our evaluation cannot statistically resolve—an architecture a hardware‑blind search would never find. The workflow itself is generic: an LLM agent explores an implementation space under real hardware limits, measuring the cost of every choice rather than assuming it.
Review