The rapid growth of digital circuit size and complexity strains traditional Electronic Design Automation (EDA) flows. Inspired by the success of large language models (LLMs) in software development, this work investigates their applicability to hardware description language (HDL) generation, focusing on VHDL where systematic studies are scarce. We introduce VHDLBench, a dataset containing over 18,500 syntax‑verified VHDL examples sourced from open‑source repositories and converted from Verilog designs.
Five 7‑billion‑parameter LLMs were fine‑tuned using the parameter‑efficient QLoRA technique, enabling deployment on resource‑constrained platforms. To rigorously assess generation quality, a three‑level evaluation pipeline was built: (1) syntax and synthesis validation to ensure code passes VHDL compilers and synthesis tools; (2) functional simulation with testbenches for behavioral correctness; (3) FPGA prototyping on Zynq SoCs to run the generated hardware.
Results show fine‑tuned models achieve up to 92% syntax correctness and 73% functional accuracy on typical design tasks, with DeepSeek‑Coder delivering the highest gains. All generated designs were successfully programmed onto real hardware, confirming operational viability beyond mere syntactic compliance.
The study demonstrates that domain‑specific data combined with lightweight fine‑tuning allows LLMs to contribute meaningfully to generative EDA workflows, opening new avenues for future hardware design automation. Review