Reinforcement learning (RL) enables adaptive autonomous decision‑making in embedded, edge and heterogeneous computing systems. FPGA and ASIC offer low latency, energy efficiency and architectural flexibility for RL deployment, yet introduce resource constraints, implementation complexity and hardware‑algorithm co‑design challenges.
This survey reviews over one hundred studies that implement RL on FPGA and ASIC, focusing on architectures, implementation strategies, performance evaluation and application domains. The literature is organized by RL families such as model‑based Markov decision processes, classic value‑based methods, deep RL, actor‑critic, policy‑gradient and multi‑agent approaches, and further classified by abstraction level, hardware realization method and target application, examining how algorithms map to reconfigurable and fixed hardware.
Unlike surveys limited to specific algorithms or platforms, this work provides a unified analysis of FPGA and ASIC implementations, covering acceleration, reconfigurable architectures, energy‑aware control and system‑level optimization. Comparative metrics include resource utilization, latency, throughput, power consumption and reported performance gains.
Finally, recurring architectural patterns, practical limitations, open challenges and future research directions are identified, offering a consolidated reference for developing and evaluating RL solutions on specialized hardware.
Review