Designing power‑electronics converters has traditionally required extensive human expertise in topology sizing, commercial component selection, circuit simulation verification, and schematic drafting. Large language models (LLMs) show promise for electronic design automation (EDA), yet applying a standalone LLM directly to board‑level schematic synthesis leads to severe engineering hallucinations such as inaccurate sizing, fabricated or mismatched part numbers, violated voltage derating, and broken topological connectivity. To address this, we present a bounded dual‑loop automated schematic synthesis framework that translates natural‑language specifications into verified, editable KiCad schematics and manufacturing deliverables. The workflow consists of six stages grouped into three functional columns: (1) requirement parsing and knowledge‑driven power‑stage synthesis covering non‑isolated Buck and Boost as well as isolated/resonant Flyback, DAB, and half‑bridge LLC topologies; (2) contract‑ and evidence‑coordinated component selection using distributor APIs and OEM datasheets, coupled with closed‑loop ngspice transient verification and stress feedback; (3) modular control‑hardware integration and multi‑format deliverable generation with native KiCad netlist round‑trip verification. End‑to‑end case studies on a 24‑36 V→12 V, 2 A Buck converter (29 positions, 83 verified terminals) and an isolated 48 V→24 V, 0.5 A Dual‑Active Bridge (DAB) converter (87 positions, 341 verified terminals) demonstrate that the framework raises component verification coverage from 22.2 % to 98.6 %, nominal‑value consistency from 0 % to 97.7 %, and SPICE simulation pass rate from 0 % to 100 % compared with a vanilla LLM baseline.
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