Automated macro placement remains a fundamental challenge in VLSI physical design. Conventional approaches rely on handcrafted proxy objectives such as estimated wirelength and perform a one-shot numerical optimization, making it hard to integrate visual layout context, codified expertise, and downstream physical feedback within a unified loop.
We introduce PlaceReasoner-Beta, a verifier‑guided multi‑agent framework that reformulates macro placement as a closed‑loop reasoning problem. A vision‑language model (VLM) planner generates candidate placements from the floorplan image, macro specifications, and connectivity; a geometric verifier enforces physical legality and expert placement principles; a physical verifier refines candidates using early implementation feedback; and a post‑route optimizer further improves promising layouts based on final PPA.
To enable reproducible evaluation, we build PlaceReasoner-Bench, a fully open end‑to‑end benchmark assembled from open RTL designs, EDA tools, and technology libraries. The benchmark comprises eight designs at two aspect ratios, yielding sixteen tasks with fixed floorplans and I/O assignments, so methods differ only in macro positions and orientations and are evaluated using routed PPA and DRC rather than pre‑route proxies.
Across all square tasks, PlaceReasoner-Beta achieves the best timing among DRC‑clean methods. It reduces post‑route TNS by 61.2% at 1:1 and 53.0% at 2:1 compared with the classical baseline. Despite never explicitly optimizing wirelength, it shortens routed wirelength on most designs, demonstrating that reasoning over spatial structure under physical‑design feedback can improve end‑to‑end layout quality beyond proxy‑objective optimization.
Review